Integrated circuits are continuously being made smaller as demand for portability, computing power, memory capacity and energy efficiency in modern electronics grows. Therefore, the size of the integrated circuit constituent features, such as electrical devices and interconnect line widths, is also decreasing continuously. The trend of decreasing feature size is evident in memory circuits or devices such as dynamic random access memory (“DRAM”), flash memory, nonvolatile memory, static random access memory (“SRAM”), ferroelectric (“FE”) memory, logic gate arrays and so forth.
For example, DRAM typically comprises millions of identical circuit elements, known as memory cells. A typical memory cell consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one binary digit (“bit”) of data. A bit can be written to a memory cell through the transistor and read by sensing charge on the reference electrode of the storage capacitor. By decreasing the sizes of these constituent electrical devices and the conducting lines that interconnect them, the sizes of the memory devices incorporating memory cells can likewise be decreased. In similar fashion, the storage capacities of these devices can be increased by fitting more memory cells into the memory devices.
As another example, flash memory (for example, electrically erasable programmable read only memory or “EEPROM”) is a type of memory that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. The memory cells include a floating gate field effect transistor capable of holding a charge. The data in a memory cell is determined by the presence or absence of charge on the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a flash memory array are typically arranged into a “NOR” architecture (in which each memory cell is directly coupled to a bit line) or a “NAND” architecture (in which memory cells are coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access). The memory cells within an erase block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
As is evident from the examples provided here, memory devices typically include large patterns or arrays of electrical devices and conductors that are used to interconnect the electrical devices. The “pitch” of such a pattern is defined as the distance between an identical point in two neighboring features in the pattern. These features are typically defined by openings in, and are spaced apart from each other by, a material such as an insulator or conductor. Thus, pitch can be understood as the sum of the width of a feature and the width of the space separating that feature from a neighboring feature.